The present disclosure relates to dynamic random access memories (“DRAMs”), and more particularly, to a method and apparatus for mapping memory bank addresses relative to memory bank retention times in DRAMs.
In a typical computing system, a memory hierarchy supports a central processing unit (“CPU”) with data storage capabilities. Generally, the type of memory device used as the primary random access memory (“RAM”) in a computing system is dynamic random access memory (“DRAM”). DRAM is comparatively low in cost and high in density, facilitating the storage of large quantities of data within a small volume of the computing system.
Unlike static random access memory (“SRAM”), which generally has a lower density than DRAM, data stored in DRAM must be refreshed periodically to prevent the data from being lost due to charge leakage from the DRAM cells. This typically results in correspondingly higher power consumptions for computing systems using DRAM.
Since data stored in DRAMs is destroyed after being idle for a period of time, DRAMs require refresh cycles to restore their data. Memory cells in DRAMs must be periodically refreshed within a certain period of time. This period of time is called the “retention time”. Depending on such factors as the chip technology and the chip temperature, the retention time may range from a few milliseconds to hundreds of milliseconds.
Each DRAM memory may be organized into arrays or banks. Data refresh is typically accomplished by accessing each row in each memory bank, one row in each bank at a time. When the memory banks are accessed to be refreshed, data stored in memory cells of the banks are read to sense-amplifiers, and immediately written back to the memory cells. A capacitor corresponding to each memory cell is thus recharged to its initial value. Such refresh cycles in DRAMs consume power, which may be at a premium in battery-powered mobile computing systems, for example.
Accordingly, what is needed is a system and method for reducing the power consumption of DRAM devices that is suitable for use in battery-powered mobile computing systems.